Lead ASIC Physical Engineer

Job Duties: 

Work as part of a dynamic, motivated, hardworking team handling block and full-chip Physical Design of complex SoCs. Your responsibilities may include handling of block for netlist to GDSII flow, full-chip STA and PV, etc. You may also lead projects including block-level PD work.


  • 6+ years of hands-on experience in ASIC physical design.
  • Extensive Experience in handling different PNR tools – Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Experience with advanced technology nodes (e.g., 7nm, 5nm, 3nm) is a plus.
  • Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR
  • Familiarity with STA (Static Timing Analysis) and EDA tools such as Synopsys Primetime.
  • Knowledge of scripting languages (e.g., Python, TCL) for automation and tool scripting.
  • Experience with low-power design techniques and power analysis tools.
  • Outstanding problem-solving skills, attention to detail, and critical thinking ability.
  • Strong leadership, communication, and teamwork skills.

Education: BE/ME/B.Tech/M.Tech/MS

Experience: 6+ years

Location: Ahmedabad

APPLY (email to info@pronesis-tech.com) (need to figure out how to implement this)