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ASIC Physical Design Services

Pronesis ASIC Physical design Services provides RTL to GSDII delivery of ASICs, SoCs and FPGAs.

  • Technology experience based on varying nodes from 180nm to 3nm with leading foundries like TSMC, Intel, Samsung, GF, Tower Semiconductor, X-Fab
  • Flow development support from Synthesis to Signoff for Synopsys, Cadence and Mentor tools.
  • RTL & Physical Synthesis
  • Full chip and Block level PNR implementation
  •  High speed and low power methodology implementation
  •  Flat & Hierarchical Floorplanning and Partitioning
  •  Place & Route
  •  Clock tree Synthesis
  •  Timing closure (STA with OCV, AOCV, POCV)
  •  Signoff Closure (Power, IR, EM, Physical Verification, Noise)
  •  Digital Power Integrity flow for Industry trusted Redhawk and Voltus tool.

1.IP/Block Hardening
Pronesis Technologies provides backend services from synthesis to GDSII for digital IP hardening. Experience on IPs such as high-speed DDR PHY controller, DLL PHY IPs, embedded FPGA IPs.

2.Digital Blocks for Analog Mixed Signal Design
Pronesis Technologies provides complete solution for digital blocks from netlist to GDSII. Experience with Analog and Mixed Signal ASICs from Flow development to PNR implementation of digital blocks. Experience includes Analog Top or Digital Top for tapeout.

3.Physical Design of High-Speed Complex SOCs
Pronesis Technologies provides physical design services of High-Speed complex SoCs. Our expertise includes Floorplanning and Power planning of blocks consisting 500+ Macros, Clock tree planning for up to 1.5GHz, Place & Route of blocks consisting of 4M+ instances, Timing closure of such complex blocks, Physical Verification, IR drop analysis and closure, etc. We have expertise on IPs such as 100 Gbps Serdes, HBM, 100G Ethernet, etc.





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