With ever increasing size of ASIC and FPGA, complexity of verification is increasing exponentially. Every small change in design is resulting in long verification cycle. As a result, 50-70% of chip development resources are now getting consumed by verification efforts. With processor now part of SoC, complexity of verification further increases.

Our team has extensive experience in taking up full responsibility or being part of larger customer team, delivering module to full-chip verification for complex chips. We have worked with simple verification environment created using simple Verilog or VHDL to full coverage driven random environment in SystemVerilog using UVM. Our team has developed reusable Verification components from scratch as well as used industry standard VIPs as part of environment to reduce time and improve quality of verification. We have verified multiple chips, pre and post silicon, to ensure highest quality working chips.

Pronesis has extensive experience of

• Verification using Verilog or VHDL
• Verification using HVLs like SystemVerilog, Vera, ‘e’, SystemC, etc.
• Verification using methodologies such as UVM, OVM, VMM, etc.